Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer

An integrated circuit (IC) comprising:

• a bulk silicon substrate;
• a layer above the substrate and including monocrystalline semiconductor material that includes germanium, the layer having a maximum vertical thickness of at most 300 nanometers (nm), the layer further having a top surface including a dislocation density of at most 1E7 per square centimeter;
• an intervening layer between the layer and the substrate, the intervening layer including monocrystalline semiconductor material and having a maximum thickness of at most 50 nm;
• a channel region above the intervening layer;
• a gate structure at least above the channel region;
• a source region adjacent the channel region;
• and
• a drain region adjacent the channel region.

An integrated circuit (IC) comprising:

• a substrate of monocrystalline silicon;
• a layer on the substrate and including monocrystalline semiconductor material that includes silicon and germanium, the germanium being at a concentration of less than 35 atomic percent, the layer having a maximum vertical thickness of less than 250 nanometers (nm), wherein an interface between the layer and the substrate includes defects, and the defects terminate within the substrate and/or in a bottom portion of the layer, such that none of the defects run to a top surface of the layer;
• a PMOS device on the layer and having a first gate structure on at least top and side surfaces of a compressively strained region comprising monocrystalline semiconductor material;
• and
• an NMOS device on the layer and having a second gate structure on at least top and side surfaces of a tensile strained region comprising monocrystalline semiconductor material.