Sensing device for high voltage applications

An integrated circuit, comprising:

• a semiconductor substrate;
• a low-voltage region included in the semiconductor substrate, the low-voltage region including:
• a low-side driver circuit configured to control a low-side switch of a power converter;
• a high-voltage region included in the semiconductor substrate, the high-voltage region including:
• a floating region of a first conductivity type;
• a high-voltage sensing device disposed in the floating region, the high-voltage sensing device including:
• a first junction-field effect transistor (JFET), the first JFET being configured to operate in pinch-off mode;
• and
• a voltage divider including:
• a first terminal coupled to a drain of the first JFET;
• a second terminal coupled to a gate of the first JFET;
• and
• a sense terminal, the voltage divider being configured to provide, on the sense terminal, a voltage indicative of a voltage differential between the drain of the first JFET and the gate of the first JFET;
• a high-side driver circuit coupled with the sense terminal, the high-side driver circuit being configured to control a high-side switch of the power converter based on the voltage on the sense terminal;
• and
• a high-voltage junction termination region surrounding the floating region, the high-voltage junction termination region including a second JFET.

An integrated circuit, comprising:

• a semiconductor substrate;
• a low-voltage region included in the semiconductor substrate, the low-voltage region including:
• a low-side driver circuit configured to control a low-side switch of a power converter;
• a high-voltage region included in the semiconductor substrate, the high-voltage region including:
• a floating region of a first conductivity type;
• a high-voltage sensing device disposed in the floating region, the high-voltage sensing device including:
• a junction-field effect transistor (JFET), the JFET being configured to operate in pinch-off mode;
• and
• a resistive-capacitive voltage divider including:
• a first terminal coupled to a drain of the JFET;
• a second terminal coupled to a gate of the JFET;
• and
• a sense terminal, the resistive-capacitive voltage divider being configured to provide, on the sense terminal, a voltage indicative of a voltage differential between the drain of the JFET and the gate of the JFET,
• the resistive-capacitive voltage divider including:
• a first capacitor coupled between the drain of the JFET and the sense terminal;
• a second capacitor coupled between the sense terminal and the gate of the JFET;
• a spiral resistive element, the sense terminal being coupled to the spiral resistive element to define a first resistor and a second resistor of the resistive-capacitive voltage divider, the first resistor being coupled between the drain of the JFET and the sense terminal, and the second resistor being coupled between the sense terminal and the gate of the JFET;
• and
• a high-side driver circuit coupled with the sense terminal, the high-side driver circuit being configured to control a high-side switch of the power converter based on the voltage on the sense terminal.