Vertical transport field effect transistor with bottom source/drain
AssigneeInternational Business Machines Corporation
InventorsHeng Wu, Gen Tsutsui, Lan Yu, Ruilong Xie
Life of this patent
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Abstract
A method for fabricating a vertical transistor device includes forming a plurality of fins on a substrate. The method further includes forming an interlevel dielectric layer on the substrate and sidewalls of each of the fins. The method further includes selectively removing the interlevel dielectric layer between adjacent fins. The method further includes laterally recessing a portion of the substrate between the adjacent fins to form a bottom source/drain cavity exposing a bottom portion of each fin and extending beyond each fin. The method further includes epitaxially growing an epitaxial growth material from the substrate and filling the bottom source/drain cavity.
Claims20
A method comprising:
- forming a plurality of fins on a substrate;
- forming an interlevel dielectric layer on the substrate and sidewalls of each of the fins;
- selectively removing the interlevel dielectric layer between adjacent fins exposing a top surface of the substrate;
- laterally recessing a portion of the substrate between the adjacent fins to form a bottom source/drain cavity in the substrate exposing a bottom surface of each fin and extending beyond each fin;
- and
- epitaxially growing an epitaxial growth material from the substrate and filling the bottom source/drain cavity.
Dependencies are inferred from the claim text.