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US 11,056,585 B2Granted
Small pitch super junction MOSFET structure and method
AssigneeIpower Semiconductor
InventorHamza Yilmaz
Life of this patent
Estimating the term…
Abstract
The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.
Claims21
A semiconductor device including a drift region that is capable of blocking voltage, comprising:
- a bottom surface and a top surface of the drift region, the bottom surface and the top surface being in electrical connection with a bottom electrode and a top electrode of the semiconductor device, respectively;
- P type regions of the drift region, extending between the top surface and the bottom surface, each P type region including a pillar with a plurality of zones, wherein each pillar is gradually expanding in the direction of the top surface so that a top zone of each pillar, which contacts the top surface, is larger than a bottom zone of each pillar, which contacts the bottom surface, the top zone being rectangular prism shape and parallel to the top surface,
- wherein the plurality of zones include varying width and varying doping levels to achieve a charge balance in each zone, and each zone comprising one or more regions with the same width and varying net doping levels;
- an N type region of the drift region surrounding the pillars, the N type region extending between the top surface and the bottom surface of the drift region, wherein the N type region is gradually expanding in the direction of the bottom surface so that a top portion of the N type region, which is adjacent the top surface, is smaller than a bottom portion of the N type region, which is adjacent the bottom surface, wherein the pillars and the N type region surrounding the pillars are repeated having opposite charge in equal magnitudes;
- and
- wherein the pillars and the N type region surrounding the pillars include multi zones with the same size and doping across a semiconductor wafer including device edges.
3 more elements
A method of manufacturing a charge balanced semiconductor device, comprising:
- forming an intrinsic epitaxial layer on top of heavily doped substrate;
- ion implanting N type dopants without mask and implanting P type dopants via mask to form a first charge balanced layer having a first P type zone and a first N type zone;
- annealing out the implantation defects at a predetermined temperature range;
- forming another intrinsic epitaxial layer on the first charge balanced layer;
- ion implanting N type dopants without mask and implanting P type dopants via mask to form a second charge balanced layer having a second P type zone and a second N type zone,
- annealing out the implantation defects at the predetermined temperature range;
- repeating the steps of forming intrinsic epitaxial layer, ion implanting and annealing until a top charge balanced layer having a top P type zone and a top N type zone is formed;
- and
- forming within the top charge balanced layer:
- a transistor body with P type dopant implantation,
- regions which are orthogonal to the top P type zone,
- a framing layer via mask by ion implantation of a P type dopant connecting the P type top zones at edge termination regions of the semiconductor device and the N type top zones are compensated by implanting P type dopants to form a subsurface lighter doped N type layer to spread potential laterally further out in the edge termination to achieve high breakdown voltage.
9 more elements
A semiconductor device including a drift region that is capable of blocking voltage, comprising:
- a bottom surface and a top surface of the drift region, the bottom surface and the top surface being in electrical connection with a bottom electrode and a top electrode of the semiconductor device, respectively;
- P type regions of the drift region, extending between the top surface and the bottom surface, each P type region including a pillar with a plurality of zones, wherein each pillar is gradually expanding in the direction of the top surface so that a top zone of each pillar, which contacts the top surface, is larger than a bottom zone of each pillar, which contacts the bottom surface, the top zone being rectangular prism shape and parallel to the top surface,
- wherein the plurality of zones include varying width and varying doping levels to achieve a charge balance in each zone, and each zone comprising one or more regions with the same width and varying net doping levels;
- an N type region of the drift region surrounding the pillars, N type region extending between the top surface and the bottom surface of the drift region, wherein the N type region is gradually expanding in the direction of the bottom surface so that a top portion of the N type region, which is adjacent the top surface, is smaller than a bottom portion of the N type region, which is adjacent the bottom surface, wherein the pillars and the N type region surrounding the pillars are repeated having opposite charge in equal magnitudes;
- a P type body layer over the top surface of the drift region;
- an N type source region positioned between the top electrode and the P type body layer;
- a trench coated with a dielectric layer, and filled with an N type poly silicon layer forming a MOS gate, aligned orthogonally with longer edges of the top zone having rectangular shape;
- and
- a drain as the bottom surface electrode for forming a vertical super junction MOSFET.
6 more elements
Dependencies are inferred from the claim text.