US 11,056,575 B2Granted

Power semiconductor device with alternating source region and body contact region and manufacturing method thereof

AssigneeMagnaChip Semiconductor, Ltd.

InventorsSoo Chang Kang, Seong Jo Hong

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Abstract

A method for manufacturing a power semiconductor device includes forming a drift region in a substrate, forming a trench in the drift region, forming a gate insulating layer in the trench, depositing a conductive material on the substrate, forming a gate electrode in the trench, forming a body region in the substrate, forming a highly doped source region in the body region, forming an insulating layer that covers the gate electrode, etching the insulating layer to open the body region, implanting a dopant into a portion of the body region to form a highly doped body contact region, so that the highly doped source region and the highly doped body contact region are alternately formed in the body region; and forming a source electrode on the highly doped body contact region and the highly doped source region.

Claims21

Dependent claims

A power semiconductor device, comprising:

a drift region formed in a substrate;
a trench formed in the drift region;
a gate insulating layer and a gate electrode formed in the trench;
a body region formed in the substrate;
a highly doped source region formed in the body region;
a highly doped body contact region formed in the body region, an area of the highly doped source region in a plan view being lamer than an area of the highly doped body contact region in the plan view;
an insulating layer formed on the gate electrode;
and
a source electrode formed on the substrate,
wherein the highly doped source region extends across a portion of an upper surface of the body region between the trench and another trench and directly contacts the body region, the trench, the another trench, the highly doped body contact region, and another highly doped body contact region formed in the body region,
wherein no highly doped body contact region is formed under the highly doped source region, and the highly doped source region and the highly doped body contact region are alternatively formed side by side in a top view,
wherein at least a portion of the source electrode protrudes inside the trench in which the gate electrode is formed, and wherein the at least a portion of the source electrode is in direct contact with the highly doped source region and the insulating layer.

9 more elements

A power semiconductor device, comprising:

a drift region formed in a substrate;
a trench formed in the drift region;
a gate insulating layer and a gate electrode formed in the trench;
a body region formed in the substrate;
a highly doped source region and a highly doped body contact region formed alternately in the body region;
an insulating layer formed on the gate electrode and the gate insulating layer;
and
a source electrode formed on the substrate,
wherein the topmost surface of the highly doped source region is coplanar with a topmost surface of the highly doped body contact region and the highly doped source region and the highly doped body contact region alternate along a longitudinal direction of the trench, perpendicular to a direction between the trench and another trench,
wherein an area of the highly doped source region in a plan view is larger than an area of the highly doped body contact region in the plan view,
wherein a topmost surface of the insulating layer is located below a topmost surface of the highly doped source region, and
wherein the insulating layer is in direct contact with the source electrode.

9 more elements

A power semiconductor device, comprising:

a drift region formed in a substrate;
a trench formed in the drift region;
a gate insulating layer and a gate electrode formed in the trench;
a body region formed in the substrate;
a highly doped source region and a highly doped body contact region formed alternately in the body region, an area of the highly doped source region in a plan view being larger than an area of the highly doped body contact region in the plan view;
an insulating layer formed on the gate electrode and the gate insulating layer;
and
a source electrode formed on the substrate,
wherein the highly doped source region extends across a portion of an upper surface of the body region, on which it is formed, between the trench and another trench, extends along a sidewall of the trench to overlap with the gate electrode, and at least a portion of the highly doped source region directly contacts the body region, the trench, and the another trench,
wherein a topmost surface of the insulating layer is located below a topmost surface of the body region, and
wherein the insulating layer is in direct contact with the source electrode.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/790,484Filed 23 Oct 2017
Priority: KR 10-2017-00156643 Feb 2017
Published: US 2018/0226495 A19 Aug 2018
Granted: 6 Jul 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 62/127
Top-view geometrical layouts of the regions or the junctions: of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
H10D 62/154
Source regions of DMOS transistors: dispositions