Nanosheet transistor with dual inner airgap spacers

A computer usable program product comprising one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices, the stored program instructions comprising:

• program instructions to receive a substrate structure having a set of nanosheet layers and a set of sacrificial layers stacked upon a substrate, the substrate structure including a p-channel region and an n-channel region;
• program instructions to etch a portion of the set of sacrificial layers to form divots within the p-channel region and the n-channel region of the set of sacrificial layers;
• program instructions to form a first liner on the p-channel region and the n-channel region, the first liner being formed of a material having a positive charge;
• removing the first liner from the p-channel region;
• program instructions to form a second liner on the p-channel region and n-channel region, the second liner being formed of a material having a negative charge;
• program instructions to selectively remove the second liner from portions of the p-channel region and n-channel region, wherein portions of the second liner within the divots substantially remain;
• program instructions to deposit a p-type epitaxy in the p-channel region to form first air gap spacers of the divots in the p-channel region;
• program instructions to selectively remove the first liner from the n-channel region, wherein portions of the first liner within the divots of the n-channel region substantially remain;
• and
• program instructions to deposit an n-type epitaxy in the n-channel region to form second air gap spacers of the divots in the n-channel region.