Split gate memory device and method of fabricating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai
Life of this patent
Estimating the term…
Abstract
The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a sacrificial spacer over a substrate and forming a select gate along a side of the sacrificial spacer. An inter-gate dielectric is formed over the select gate and the sacrificial spacer. A memory gate layer is formed over the inter-gate dielectric and the sacrificial spacer. The memory gate layer is laterally separated from the sacrificial spacer by the select gate. The memory gate layer is etched to define a memory gate having a topmost point below a top of the sacrificial spacer.
Claims20
A method of forming a memory cell, comprising:
- forming a sacrificial spacer over a substrate;
- forming a select gate along a side of the sacrificial spacer;
- forming an inter-gate dielectric over the select gate and the sacrificial spacer;
- forming a memory gate layer over the inter-gate dielectric and the sacrificial spacer, wherein the memory gate layer is laterally separated from the sacrificial spacer by the select gate;
- and
- etching the memory gate layer to define a memory gate having a topmost point below a top of the sacrificial spacer.
A method of forming an integrated chip, comprising:
- forming a spacer over a substrate;
- forming a select gate along a first side of the spacer;
- forming an inter-gate dielectric over the select gate and the spacer;
- forming a memory gate layer over the inter-gate dielectric;
- and
- performing a first etching process to etch the memory gate layer and to define a memory gate having a top below tops of the spacer and the select gate.
A method of forming an integrated chip, comprising:
- forming a first sacrificial structure and a second sacrificial structure over a substrate;
- forming a plurality of select gates along opposing sides of the first sacrificial structure and the second sacrificial structure;
- forming an inter-gate dielectric over the plurality of select gates, the first sacrificial structure, and the second sacrificial structure;
- forming a memory gate layer over the inter-gate dielectric;
- and
- etching the memory gate layer to define a plurality of memory gates respectively having a topmost point below a top of the first sacrificial structure or the second sacrificial structure, wherein the plurality of memory gates are disposed between closest neighboring ones of the plurality of select gates and are separated from one another by a distance that is between the closest neighboring ones of the plurality of select gates.
Dependencies are inferred from the claim text.