Flash memory device and method

A method to form a flash memory device, comprising:

• providing a semiconductor substrate;
• forming a lower dielectric layer over the semiconductor substrate in a first region of the semiconductor substrate;
• forming an upper dielectric layer which will form a flash memory gate electrode;
• forming another lower dielectric layer on the upper dielectric layer, wherein forming alternating lower and upper dielectric layers forms a dielectric layer stack
• forming a first opening through the dielectric layer stack,
• forming one or more multi stack charge trap layers in the first opening,
• wherein the one or more multi stack charge trap layers comprise an oxide-nitride-nitride-oxide (ONNO) stack wherein:
• the ONNO stack comprises a multi-layer charge-trapping region, comprising a NN portion of the ONNO stack, wherein
• a first nitride region of the NN portion of the ONNO stack comprises a silicon component, an oxygen component, and a nitrogen component, and the nitrogen and silicon components of said first N region have increasing concentrations moving away from a tunnel oxide and toward a blocking oxide until a maximum is reached;
• the second nitride region of the NN portion of the ONNO stack comprises a silicon component, an oxygen component, and a nitrogen component, and the nitrogen and silicon components of said second N region have decreasing concentrations moving away from the tunnel oxide and toward the blocking oxide;
• removing a blocking dielectric layer, a charge storing layer and a tunnel dielectric layer from a bottom surface of the first opening;
• forming a polysilicon layer as a channel region of the flash memory device;
• forming flash memory gate electrodes, wherein the gate electrodes comprise a high work function metal material;
• and
• forming metal oxide semiconductor (MOS) logic devices in a different location from the flash memory gates, wherein the MOS logic devices comprise the same materials as the flash memory device.