Semiconductor device, semiconductor module, and packaged semiconductor device

A semiconductor device, comprising:

• a semiconductor substrate that includes silicon and a first conductivity-type impurity;
• a low-concentration impurity layer that is in contact with a front surface of the semiconductor substrate, and includes a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate;
• a backside electrode that is in contact with a back surface of the semiconductor substrate, and includes a metal material;
• a first vertical metal-oxide semiconductor (MOS) transistor that is located in a first region in the low-concentration impurity layer;
• and
• a second vertical MOS transistor that is located in a second region adjacent to the first region in the low-concentration impurity layer in a plan view of the semiconductor substrate,
• wherein the first vertical MOS transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer,
• the second vertical MOS transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer,
• the semiconductor substrate serves as a common drain region of a first drain region of the first vertical MOS transistor and a second drain region of the second vertical MOS transistor,
• a ratio of a thickness of the first source electrode to a thickness of the backside electrode is 0.28 or less, and
• a ratio of a thickness of the second source electrode to the thickness of the backside electrode is 0.28 or less.

A semiconductor device, comprising:

• a semiconductor substrate that includes silicon and a first conductivity-type impurity;
• a low-concentration impurity layer that is in contact with a front surface of the semiconductor substrate, and includes a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate;
• a backside electrode that is in contact with a back surface of the semiconductor substrate, and includes a metal material;
• a first vertical metal-oxide semiconductor (MOS) transistor that is located in a first region in the low-concentration impurity layer;
• and
• a second vertical MOS transistor that is located in a second region adjacent to the first region in the low-concentration impurity layer in a plan view of the semiconductor substrate,
• wherein the first vertical MOS transistor includes a plurality of first source electrodes and a first gate electrode on a surface of the low-concentration impurity layer,
• the second vertical MOS transistor includes a plurality of second source electrodes and a second gate electrode on the surface of the low-concentration impurity layer,
• the semiconductor substrate serves as a common drain region of a first drain region of the first vertical MOS transistor and a second drain region of the second vertical MOS transistor, and
• a third source electrode included in the plurality of the first source electrodes and a fourth source electrode included in the plurality of the second source electrodes are source electrodes disposed closest to a boundary between the first region and the second region, the third source electrode and the fourth source electrode extending along an entirety of the boundary.

A semiconductor device, comprising:

• a semiconductor substrate that includes silicon and a first conductivity-type impurity;
• a low-concentration impurity layer that is in contact with a front surface of the semiconductor substrate, and includes a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate;
• a backside electrode that is in contact with a back surface of the semiconductor substrate, and includes a metal material;
• a first vertical metal-oxide semiconductor (MOS) transistor that is located in a first region in the low-concentration impurity layer;
• and
• a second vertical MOS transistor that is located in a second region adjacent to the first region in the low-concentration impurity layer in a plan view of the semiconductor substrate,
• wherein the first vertical MOS transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer,
• the second vertical MOS transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer,
• the semiconductor substrate serves as a common drain region of a first drain region of the first vertical MOS transistor and a second drain region of the second vertical MOS transistor,
• the first source electrode comprises, between (i) a boundary of the first region and the second region and (ii) a first opposite end which is an end of the first region that is opposite to the boundary, a plurality of first source electrodes aligned in a direction that crosses the boundary,
• the first gate electrode is disposed at a position that is near a center of the first opposite end in a direction parallel to the boundary and between a pair of the plurality of first source electrodes in the direction parallel to the boundary,
• a center point of the first gate electrode is disposed at a position that is offset toward the first opposite end from a boundary-side end of a first source electrode farthest from the boundary, in the first region, the boundary-side end being an end of the first source electrode that is closest to the boundary,
• the second source electrode comprises, between the boundary and a second opposite end which is an end of the second region that is opposite to the boundary, a plurality of second source electrodes aligned in a direction that crosses the boundary,
• the second gate electrode is disposed at a position that is near a center of the second opposite end in a direction parallel to the boundary and between a pair of the plurality of second source electrodes in the direction parallel to the boundary, and
• a center point of the second gate electrode is disposed at a position that is offset toward the second opposite end from a boundary-side end of a second source electrode farthest from the boundary, in the second region, the boundary-side end being an end of the second source electrode that is closest to the boundary.