Silicided source/drain terminals for field-effect transistors
AssigneeGlobalFoundries Dresden Module One Limited Liability Company & Co. KG
InventorsMaximilian Ludwig Drescher, Violetta Sessi
Life of this patent
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Abstract
Structures including field-effect transistors and methods of forming a structure including field-effect transistors. A first field-effect transistor includes a first source/drain terminal and a second source/drain terminal, and a second field-effect transistor includes a third source/drain terminal and a fourth source/drain terminal. The first source/drain terminal and the second source/drain terminal each include a fully-silicided section located at and above a top surface of a semiconductor layer. The third source/drain terminal and the fourth source/drain terminal each include a partially-silicided section located over the top surface of the semiconductor layer.
Claims20
A structure comprising:
- a semiconductor layer having a top surface;
- a first field-effect transistor including a first source/drain terminal and a second source/drain terminal, the first source/drain terminal and the second source/drain terminal each including a first fully-silicided section located at and above the top surface of the semiconductor layer and a second fully-silicided section located at and below the top surface of the semiconductor layer;
- and
- a second field-effect transistor including a third source/drain terminal and a fourth source/drain terminal, the third source/drain terminal and the fourth source/drain terminal each including a first partially-silicided section located above the top surface of the semiconductor layer.
A structure comprising:
- a semiconductor layer having a top surface;
- a first field-effect transistor including a first source/drain terminal and a second source/drain terminal, the first source/drain terminal and the second source/drain terminal each including a first fully-silicided section located at and above the top surface of the semiconductor layer;
- a second field-effect transistor including a third source/drain terminal and a fourth source/drain terminal, the third source/drain terminal and the fourth source/drain terminal each including a first partially-silicided section located above the top surface of the semiconductor layer;
- and
- a third field-effect transistor including a fifth source/drain terminal and a sixth source/drain terminal, the fifth source/drain terminal and the sixth source/drain terminal each including a second partially-silicided section located above the top surface of the semiconductor layer,
- wherein the first field-effect transistor is a p-type field-effect transistor, an n-type field-effect transistor, or an ambipolar field-effect transistor, the second field-effect transistor is a p-type field-effect transistor, and the third field-effect transistor is an n-type field-effect transistor.
A method comprising:
- forming a first source/drain terminal and a second source/drain terminal of a first field-effect transistor that each include a first fully-silicided section located at and above a top surface of a semiconductor layer;
- and
- forming a third source/drain terminal and a fourth source/drain terminal of a second field-effect transistor that each include a first partially-silicided section located above the top surface of the semiconductor layer,
- wherein the first fully-silicided section of the first source/drain terminal comprises a first section of a silicide layer, the first fully-silicided section of the second source/drain terminal comprises a second section of the silicide layer, and the first partially-silicided section of the third source/drain terminal includes a third section of the silicide layer, and the first partially-silicided section of the fourth source/drain terminal includes a fourth section of the silicide layer.
Dependencies are inferred from the claim text.