Self-aligned gate contact integration with metal resistor
AssigneeInternational Business Machines Corporation
InventorsXin Miao, Richard A. Conti, Ruilong Xie, Kangguo Cheng
Life of this patent
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Abstract
A middle-of-line (MOL) structure is provided and includes device and resistive memory (RM) regions. The device region includes trench silicide (TS) metallization, a first interlayer dielectric (ILD) portion and a first dielectric cap portion disposed over the TS metallization and the first ILD portion. The RM region includes a second dielectric cap portion, a second ILD portion and an RM resistor interposed between the second dielectric cap portion and the second ILD portion.
Claims8
A method of fabricating a middle-of-line (MOL) structure comprising a device region and a resistive memory (RM) region, the method comprising:
- forming lower source/drain (S/D) metallization interleaved with gate elements in the device region;
- recessing interlayer dielectric (ILD) in the device region and RM region;
- disposing an RM resistor over the recessed ILD in the RM region;
- recessing the lower S/D metallization in the device region;
- forming a dielectric cap over the recessed lower S/D metallization and the recessed ILD in the device region and over the RM resistor in the RM region;
- forming first S/D contacts to the S/D metallization in the device region;
- forming second S/D contacts to the gate elements in the device region;
- and forming an S/D contact to the RM resistor in the RM region.
Dependencies are inferred from the claim text.