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US 11,056,535 B2Granted
Non-volatile memory element arrays in a wheatstone bridge arrangement
AssigneeGlobalFoundries U.S. Inc.
InventorsAjey Poovannummoottil Jacob, Amogh Agrawal
Life of this patent
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Abstract
Structures for a bitcell of a non-volatile memory and methods of fabricating and using such structures. Non-volatile memory elements are arranged in a Wheatstone bridge arrangement having a first terminal and a second terminal. A first field-effect transistor is coupled with the first terminal of the Wheatstone bridge arrangement, and a second field-effect transistor is coupled with the second terminal of the Wheatstone bridge arrangement.
Claims20
A structure for a bitcell, the structure comprising:
- a plurality of non-volatile memory elements arranged in a Wheatstone bridge arrangement having a first terminal and a second terminal;
- a first field-effect transistor coupled with the first terminal;
- a second field-effect transistor coupled with the second terminal;
- and
- an interconnect structure that is positioned over the first field-effect transistor and the second field-effect transistor, the interconnect structure including a bit line coupled by the first field-effect transistor with the first terminal and a complementary bit line coupled by the second field-effect transistor with the second terminal,
- wherein the non-volatile memory elements are positioned in the interconnect structure.
3 more elements
A method of forming a structure for a bitcell, the method comprising:
- forming a first field-effect transistor and a second field-effect transistor;
- forming a plurality of non-volatile memory elements in an interconnect structure that is positioned over the first field-effect transistor and the second field-effect transistor, wherein the non-volatile memory elements are arranged in a Wheatstone bridge arrangement;
- forming a bit line in the interconnect structure that is coupled by the first field-effect transistor with a first terminal of the Wheatstone bridge arrangement;
- and
- forming a complementary bit line in the interconnect structure that is coupled by the second field-effect transistor with a second terminal of the Wheatstone bridge arrangement.
2 more elements
A method comprising:
- placing a plurality of non-volatile memory elements having a Wheatstone bridge arrangement in a first combination of parallel states and anti-parallel states to write a first memory state of a bitcell;
- and
- placing the non-volatile memory elements having the Wheatstone bridge arrangement in a second combination of parallel states and anti-parallel states to write a second memory state of the bitcell,
- wherein the first combination of parallel states and anti-parallel states and the second combination of parallel states and anti-parallel states are each provided by a two-step write operation in which a first biasing step with a first current provides the parallel states and a second biasing step with a second current provides the anti-parallel states, and the first current and the second current each include a first portion provided from a drive line and a second portion provided by a transistor.
1 more element
Dependencies are inferred from the claim text.