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US 11,056,534 B2Granted
One selector one resistor MRAM crosspoint memory array fabrication methods
AssigneeSanDisk Technologies LLC
InventorsLei Wan, Tsai-Wei Wu, Jordan A. Katine
Life of this patent
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Abstract
A memory array is provided that includes a first memory level having a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element, and a plurality of vias, each of the vias coupled in series with a corresponding one of the memory cells.
Claims16
A memory array comprising:
- a first memory level comprising:
- a plurality of memory cells each comprising a corresponding magnetic memory element coupled in series with a corresponding selector element;
- a plurality of vias, each of the vias coupled in series with a corresponding one of the memory cells;
- a plurality of word lines and a plurality of bit lines, wherein each memory cell is disposed between one of the plurality of word lines and one of the plurality of bit lines,
- wherein the plurality of memory cells comprise:
- a first memory cell disposed below a corresponding one of the vias;
- and
- a second memory cell disposed above a corresponding one of the vias.
5 more elements
A method of forming a memory array, the method comprising:
- forming a plurality of first memory cell pillars, each first memory cell pillar comprising a corresponding first magnetic material layer structure and a corresponding first selector element;
- forming a first dielectric material layer around each first memory cell pillar;
- forming first interstices between adjacent first memory cell pillars;
- forming first vias in the first interstices;
- forming a plurality of second memory cell pillars, each second memory cell pillar comprising a corresponding second magnetic material layer structure and a corresponding second selector element;
- forming a second dielectric material layer around each second memory cell pillar;
- forming second interstices between adjacent second memory cell pillars;
- and
- forming second vias in the second interstices,
- wherein each second memory cell pillar is disposed over a corresponding one of the first vias, and each first memory cell pillar is disposed under a corresponding one of the second vias.
7 more elements
Dependencies are inferred from the claim text.