Monolithic thin film elements and performance electronics, solar powered systems and fabrication
AssigneeThe Regents of the University of California
InventorsShadi A. Dayeh, Yun Goo Ro, Namseok Park, Atsunori Tanaka, Siarhei Vishniakou, Ahmed Youssef, James Buckwalter, Cooper Levy
Life of this patent
Estimating the term…
Abstract
Methods and devices that monolithically integrate thin film elements/devices, e.g., environmental sensors, batteries and biosensors, with high performance integrated circuits, i.e., integrated circuits formed in a high quality device layer. Preferred embodiments further monolithically integrate a solar cell array. Preferred embodiments provide pin-size and integrated solar powered wearable electronic, ionic, molecular, radiation, etc. sensors and circuits.
Claims17
A monolithically integrated device, comprising,
- a polymer base layer;
- an oxide layer adhered to the polymer base layer;
- a CMOS circuitry epitaxial layer that does not exceed 200 nm in thickness on top of the oxide layer;
- a polymer dielectric layer on top of the CMOS circuitry epitaxial layer, the polymer dielectric layer having a thickness in the range of 2 μm to 10 μm;
- a thin film device layer formed on the polymer dielectric layer, the thin film device layer having thickness of less than 200 nm;
- contact vias through the polymer dielectric layer;
- interconnect metal in the contact vias connecting the CMOS circuitry to the thin film device layer, wherein a total thickness of the monolithically integrated device is less than ˜50 μm thick.
A monolithically integrated device, comprising:
- a CMOS circuitry epitaxial layer including a CMOS circuit;
- a polymer dielectric layer on top of the CMOS circuitry epitaxial layer covering the CMOS circuit, the polymer dielectric layer having a thickness in the range of 2 μm to 10 μm;
- doped microwires extending from the CMOS circuitry epitaxial layer extending through the polymer dielectric layer defining a shallow solar cell junction therein, wherein the solar cell junction depth is 60 nm-100 nm;
- and
- connection between the solar cell junction and the CMOS circuitry to power the CMOS circuitry, wherein a total thickness of the monolithically integrated device is less than −50 μm thick.
Dependencies are inferred from the claim text.