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US 11,056,515 B2Granted
Logic circuit and semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
Life of this patent
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Abstract
To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.
Claims2
A method for manufacturing a liquid crystal display device comprising:
- the liquid crystal display device comprising:
- a driver circuit comprising first to eighth transistors, a first capacitor, and a second capacitor,
- a pixel electrically connected to the driver circuit;
- wherein each of the first to eighth transistors comprises an oxide semiconductor layer containing In, Ga, and Zn,
- wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
- wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
- wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the second transistor,
- wherein a first electrode of the first capacitor is electrically connected to the gate of the first transistor,
- wherein a second electrode of the first capacitor is electrically connected to the one of the source and the drain of the first transistor,
- wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
- wherein one of a source and a drain of the seventh transistor is electrically connected to a gate of the fifth transistor,
- wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the sixth transistor,
- wherein a first electrode of the second capacitor is electrically connected to the gate of the fifth transistor,
- wherein a second electrode of the second capacitor is electrically connected to the one of the source and the drain of the fifth transistor,
- wherein the other of the source and the drain of the second transistor and the other of the source and the drain of the sixth transistor are electrically connected to a first wiring,
- wherein a first signal is output from the one of the source and the drain of the first transistor,
- wherein a second signal is output from the one of the source and the drain of the fifth transistor,
- wherein the other of the source and the drain of the third transistor and the other of the source and the drain of the eighth transistor are electrically connected to a second wiring, and
- wherein the other of the source and the drain of the fourth transistor and the other of the source and the drain of the seventh transistor are electrically connected to a third wiring,
- the method comprising a step of forming each of the first to eighth transistors comprising:
- forming the oxide semiconductor layer over a gate electrode with a gate insulating film interposed therebetween;
- performing a first heat treatment on the oxide semiconductor layer;
- forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer after performing the first heat treatment;
- forming an oxide insulating layer over the source electrode layer and the drain electrode layer, the oxide insulating layer being in contact with a part of the oxide semiconductor layer;
- and
- performing a second heat treatment after forming the oxide insulating layer,
- wherein a temperature of the first heat treatment is higher than a temperature of the second heat treatment.
24 more elements
A method for manufacturing a liquid crystal display device comprising:
- the liquid crystal display device comprising:
- a driver circuit comprising first to eighth transistors, a first capacitor, and a second capacitor,
- a pixel electrically connected to the driver circuit;
- wherein each of the first to eighth transistors comprises an oxide semiconductor layer containing In, Ga, and Zn,
- wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
- wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
- wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the second transistor,
- wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor,
- wherein a first electrode of the first capacitor is electrically connected to the gate of the first transistor,
- wherein a second electrode of the first capacitor is electrically connected to the one of the source and the drain of the first transistor,
- wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
- wherein one of a source and a drain of the seventh transistor is electrically connected to a gate of the fifth transistor,
- wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the sixth transistor,
- wherein a gate of the seventh transistor is electrically connected to a gate of the eighth transistor,
- wherein a first electrode of the second capacitor is electrically connected to the gate of the fifth transistor,
- wherein a second electrode of the second capacitor is electrically connected to the one of the source and the drain of the fifth transistor,
- wherein the other of the source and the drain of the second transistor and the other of the source and the drain of the sixth transistor are electrically connected to a first wiring,
- wherein a first signal is output from the one of the source and the drain of the first transistor,
- wherein a second signal is output from the one of the source and the drain of the fifth transistor,
- wherein the other of the source and the drain of the third transistor and the other of the source and the drain of the eighth transistor are electrically connected to a second wiring, and
- wherein the other of the source and the drain of the fourth transistor and the other of the source and the drain of the seventh transistor are electrically connected to a third wiring,
- the method comprising a step of forming each of the first to eighth transistors comprising:
- forming the oxide semiconductor layer over a gate electrode with a gate insulating film interposed therebetween;
- performing a first heat treatment on the oxide semiconductor layer;
- forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer after performing the first heat treatment;
- forming an oxide insulating layer over the source electrode layer and the drain electrode layer, the oxide insulating layer being in contact with a part of the oxide semiconductor layer;
- and
- performing a second heat treatment after forming the oxide insulating layer,
- wherein a temperature of the first heat treatment is higher than a temperature of the second heat treatment.
26 more elements
Dependencies are inferred from the claim text.