Memory arrays and methods used in forming a memory array

A memory array comprising:

• a vertical stack comprising alternating insulative tiers and wordline tiers, the wordline tiers comprising gate regions of individual memory cells, the gate regions individually comprising part of a wordline in individual of the wordline tiers;
• channel material extending elevationally through the insulative tiers and the wordline tiers;
• the individual memory cells comprising a memory structure laterally between the gate region and the channel material;
• individual of the wordlines comprising laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions, the individual laterally-outer longitudinal-edge portions projecting upwardly and downwardly relative to its laterally-adjacent laterally-inner portion;
• and
• the individual laterally-outer longitudinal-edge portions comprising multiple up-projections projecting upwardly at an angle from an immediately-laterally-adjacent upper surface and having multiple down-projections projecting downwardly at an angle from an immediately-laterally-adjacent lower surface, immediately-adjacent of the multiple up-projections being laterally-spaced relative one another, immediately-adjacent of the multiple down-projections being laterally-spaced relative one another.