Semiconductor memory device including vertical barrier

A semiconductor memory device comprising:

• a dummy stack structure including a first stack structure and a second stack structure formed on the first stack structure;
• a cell stack structure surrounding the dummy stack structure;
• a vertical barrier disposed at a boundary between the cell stack structure and the dummy stack structure, the vertical barrier including a first part formed on a sidewall of the first stack structure and a second part formed on a sidewall of the second stack structure;
• and
• a source structure disposed under the vertical barrier, and surrounding a protrusion part of a lower part of the vertical barrier,
• wherein a sectional area of the first part of the vertical barrier is greater than a sectional area of the second part of the vertical barrier at a height at which a boundary between the first stack structure and the second stack structure is disposed, and
• wherein the source structure includes:
• a source layer overlapped by the cell stack structure;
• and
• a dummy source stack structure overlapped by the dummy stack structure.