Semiconductor memory device

A semiconductor memory device comprising:

• a lower structure including a first region and a second region;
• a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on the first region of the lower structure;
• a channel structure penetrating the gate stack structure;
• a dielectric stack structure including first material layers and second material layers, which are alternately stacked in the vertical direction on the second region of the lower structure;
• and
• capacitor electrodes disposed in the dielectric stack structure, the capacitor electrodes extending substantially in parallel to the channel structure,
• wherein the capacitor electrodes include:
• first capacitor electrodes connected to a first electrode line to which a first voltage is applied;
• and
• second capacitor electrodes connected to a second electrode line to which a second voltage lower than the first voltage is applied.