Memory arrays and methods used in forming a memory array

A method used in forming a memory array, comprising:

• forming conductive material of a conductive tier atop a substrate;
• etching openings into the conductive material, multiple of the openings being grouped circumferentially around individual string locations in a horizontal cross-section;
• forming an insulator tier atop the conductive tier, the insulator tier comprising insulator material that extends downwardly into the openings in the conductive material of the conductive tier;
• forming a stack comprising vertically-alternating insulative tiers and wordline tiers above the insulator tier;
• and
• forming strings comprising channel material through the insulative tiers and the wordline tiers and into the insulator tier in the string locations, the channel material of the strings being directly electrically coupled to the conductive material in the conductive tier.

A memory array comprising:

• a conductive tier comprising openings therein;
• an insulator tier atop the conductive tier, the insulator tier comprising insulator material that extends downwardly into the openings in the conductive tier, multiple of the openings in the conductive tier and the insulator material therein being laterally spaced relative one another circumferentially around individual of the strings in a horizontal cross-section;
• a stack comprising vertically-alternating insulative tiers and wordline tiers above the insulator tier;
• and
• strings comprising channel material extending through the insulative tiers and the wordline tiers, the channel material of the strings being directly electrically coupled to conductive material in the conductive tier.

A memory array comprising:

• a conductive tier comprising openings therein;
• an insulator tier atop the conductive tier, the insulator tier comprising insulator material that extends downwardly into and completely fills the openings in the conductive tier, multiple of the openings in the conductive tier and the insulator material therein being laterally spaced relative one another circumferentially around individual of the strings in a horizontal cross-section;
• a stack comprising vertically-alternating insulative tiers and wordline tiers above the insulator tier;
• strings comprising channel material extending through the insulative tiers and the wordline tiers and into the insulator tier, the channel material of the strings being directly electrically coupled to conductive material in the conductive tier, the strings being everywhere laterally spaced from the openings in the conductive tier and the insulator material therein, the strings comprising:
• the channel material extending elevationally through the insulative tiers and the wordline tiers;
• insulative charge-passage material in the wordline tiers laterally outward of the channel material;
• a storage region in the wordline tiers laterally outward of the insulative charge-passage material;
• and
• a charge-blocking region in the wordline tiers laterally outward of the storage region;
• and
• said multiple being at least 3 in number;
• said multiple are shared by immediately laterally adjacent of the individual strings.

A method used in forming a memory array, comprising:

• forming conductive material of a conductive tier atop a substrate;
• etching openings into the conductive material, the openings being grouped around individual string locations;
• forming an insulator tier atop the conductive tier, the insulator tier comprising insulator material that extends downwardly into the openings in the conductive material of the conductive tier;
• forming a stack comprising vertically-alternating insulative tiers and wordline tiers above the insulator tier;
• and
• forming strings comprising channel material through the insulative tiers and the wordline tiers and into the insulator tier in the string locations, the channel material of the strings being directly electrically coupled to the conductive material in the conductive tier;
• wherein the grouped openings and insulator material therein are equally spaced around the individual string locations and around individual of the strings;
• and
• wherein, relative to being grouped, the openings and insulator material therein in individual of the groups are shared by immediately laterally adjacent of the individual groups.

A memory array comprising:

• a conductive tier comprising openings therein;
• an insulator tier atop the conductive tier, the insulator tier comprising insulator material that extends downwardly into the openings in the conductive tier, the openings in the conductive tier and the insulator material therein being laterally spaced relative one another in a horizontal cross-section;
• a stack comprising vertically-alternating insulative tiers and wordline tiers above the insulator tier;
• strings comprising channel material extending through the insulative tiers and the wordline tiers, the channel material of the strings being directly electrically coupled to conductive material in the conductive tier;
• wherein,
• the strings comprise:
• the channel material extending elevationally through the insulative tiers and the wordline tiers;
• insulative charge-passage material in the wordline tiers laterally outward of the channel material;
• a storage region in the wordline tiers laterally outward of the insulative charge-passage material;
• and
• a charge-blocking region in the wordline tiers laterally outward of the storage region;
• and
• multiple of the openings in the conductive tier and the insulator material therein are laterally outward of individual of the strings;
• wherein said multiple surround the individual strings and are at least 3 in number;
• and
• wherein relative to surround, said multiple are shared by immediately laterally adjacent of the individual strings.