Integrated assemblies having bitline contacts, and methods of forming integrated assemblies

A method of forming an integrated assembly, comprising:

• providing a construction comprising a memory-array-region, and comprising a peripheral region proximate the memory-array-region;
• the construction including a base-semiconductor-material within the memory-array-region and within the peripheral region;
• forming trenches extending into the base-semiconductor-material of the memory-array-region;
• a cross-section along the memory-array-region including a paired-memory-cell-region having two neighboring trenches extending into the base-semiconductor-material;
• the trenches being a first trench and a second trench;
• a first pillar of the base-semiconductor-material being on one side of the first trench;
• a second pillar of the base-semiconductor-material being between the first and second trenches, and being on an opposing side of the first trench from the first pillar of the base-semiconductor-material;
• a third pillar of the base-semiconductor-material being on an opposing side of the second trench from the second pillar of the base-semiconductor-material;
• the first and third pillars of the base-semiconductor-material comprising first and second charge-storage-device-contact-locations, respectively;
• the second pillar of the base-semiconductor-material comprising a bitline-contact-location;
• forming a first wordline within the first trench, and forming a second wordline within the second trench;
• the first wordline comprising a first gate along the cross-section, and the second wordline comprising a second gate along the cross-section;
• the first gate gatedly coupling the bitline-contact-location with the first charge-storage-device-contact-location, and the second gate gatedly coupling the bitline-contact-location with the second charge-storage-device-contact-location;
• forming a stack having a first a portion over the memory-array-region and having a second portion over the peripheral region;
• the stack including an insulative material over a first semiconductor material, and including a second semiconductor material over the insulative material;
• the first and second semiconductor materials within the stack not being conductively-doped and instead being in a nonconductive configuration;
• conductively doping the first and second semiconductor materials of the second portion of the stack while leaving the first and second semiconductor materials of the first portion of the stack in the nonconductive configuration;
• removing the second semiconductor material and the insulative material from the first portion of the stack;
• incorporating the conductively-doped first semiconductor material, the insulative material and the conductively-doped second semiconductor material into one or more transistor gates associated with the peripheral region;
• forming a bitline coupled with the bitline-contact-location;
• and
• forming charge-storage devices coupled with the charge-storage-device-contact-locations.