Dense memory arrays utilizing access transistors with back-side contacts

An integrated circuit (IC) package, the IC package comprising:

• an IC die;
• and
• a further component, coupled to the IC die,
• where the IC die includes:
• a first plateline and a second plateline in a first layer,
• a plurality of memory cells in a second layer, an individual memory cell comprising a transistor and a capacitor, where the transistor includes a first source/drain (S/D) region, a second S/D region, and a channel material between the first S/D region and the second S/D region, and where the capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode coupled to the first S/D region, and
• a bitline in a third layer, where the second layer is between the first layer and the third layer,
• where the first plateline is coupled to the second capacitor electrode of a first memory cell of the plurality of memory cells, the second plateline is coupled to the second capacitor electrode of a second memory cell of the plurality of memory cells, and the bitline is coupled to each of the second S/D region of the transistor of the first memory cell and the second S/D region of the transistor of the second memory cell.