Semiconductor device with electrostatic discharge protection

A semiconductor device comprising:

• a P-type substrate;
• a P-type well region, disposed on the P-type substrate, comprising source regions and drain regions each spaced apart from the other;
• an N-type well region disposed and spaced apart from the P-type well region on the P-type substrate, the N-type well region comprising the source regions, and the P-type well region comprising the drain regions;
• an N-type guard ring region disposed around perimeters of the P-type well region and the N-type well region;
• an insulating layer disposed to around the P-type well region and the N-type well region on the N-type guard ring region;
• a poly gate disposed, around the perimeters of the P-type well region and the N-type well region, respectively, on the insulating layer;
• and
• a bulk region disposed on the N-type guard ring region adjacent the poly gate.

A semiconductor device with electrostatic discharge protection comprising:

• a deep well region;
• a well region, disposed in the deep well region, comprising source regions and drain regions each spaced apart from the other, respectively;
• an insulating layer disposed around a perimeter of the well region on the deep well region;
• a poly gate disposed around the perimeter of the well region on the insulating layer;
• and
• a bulk region disposed on the deep well region adjacent the poly gate.

A semiconductor device, comprising:

• a P-type well region comprising a well tap region, a source region, a gate electrode, and a drain region;
• an N-type deep well region disposed around the P-type well region;
• an insulating layer disposed, around the perimeter of the P-type well region, on the N-type deep well region;
• and
• a poly gate disposed, around the perimeter of the P-type well region, on the insulating layer.