Metal gate structure cutting process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShiang-Bau Wang, Ryan Chia-Jen Chen, Shu-Yuan Ku, Ming-Ching Chang
Life of this patent
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Abstract
Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
Claims20
A semiconductor device, comprising:
- a first gate structure and a second gate structure disposed in an interlayer dielectric (ILD) layer disposed on a substrate, wherein each of the first gate structure and the second gate structure comprises a gate dielectric and a gate electrode;
- an isolation structure disposed between the first gate structure and the second gate structure, wherein the ILD layer circumscribes a perimeter of the isolation structure;
- and
- a dielectric structure disposed between the ILD layer and the isolation structure, wherein a bottom surface of the isolation structure is closer to the substrate than a bottom surface of the dielectric structure, wherein the isolation structure directly contacts the gate electrode of the first gate structure.
A semiconductor device, comprising:
- a first gate structure and a second gate structure;
- a first isolation structure interposed between an end of the first gate structure and an end of the second gate structure, wherein the first isolation structure extends over a shallow trench isolation interposed between two fins, wherein the first isolation structure has a first thickness at a first location and has a second thickness at a second location, wherein the first thickness is less than the second thickness;
- a second isolation structure along opposing sidewalls of the first gate structure and the second gate structure;
- and
- a third isolation structure interposed between the first isolation structure and the second isolation structure, wherein the third isolation structure does not separate the first isolation structure from the first gate structure.
A semiconductor device, comprising:
- a first transistor including a first source/drain region, a second source/drain region, a first gate structure extending along sidewalls of a first fin, the first gate structure extending over a first shallow trench isolation;
- a second transistor including a third source/drain region, a fourth source/drain region, a second gate structure extending along sidewalls of a second fin, the second gate structure extending over the first shallow trench isolation, the first gate structure and the second gate structure being aligned along a first longitudinal axis;
- a first isolation structure contacting the first gate structure and the second gate structure;
- a second isolation structure over the first source/drain region and the third source/drain region;
- and
- a third isolation structure interposed between the first isolation structure and the first source/drain region and between the first isolation structure and the third source/drain region, the third isolation structure extending along a sidewall of the first isolation structure, the sidewalls of the first isolation structure being parallel to current flow between the first source/drain region and the second source/drain region.
Dependencies are inferred from the claim text.