Method of manufacturing fan-out wafer level package

A method of manufacturing a semiconductor package, the method comprising:

• providing a sacrificial layer, a redistribution wiring layer, and a plurality of semiconductor chips provided on the redistribution wiring layer, which are sequentially stacked on a carrier substrate;
• providing a mold layer provided on the plurality of semiconductor chips to form a wafer level stack;
• removing the sacrificial layer and the carrier substrate from the wafer level stack to expose a lower surface of the redistribution wiring layer;
• and
• dicing the wafer level stack to form the semiconductor package comprising at least one of the plurality of semiconductor chips,
• wherein the mold layer is provided on an upper surface and a side surface of each of the plurality of semiconductor chips, an upper surface and a side surface of the redistribution wiring layer, and a portion of an upper surface of the sacrificial layer,
• wherein the wafer level stack comprises a cross-sectional surface having a stepped shape, and
• wherein the providing of the redistribution wiring layer comprises:
• providing a conductive layer on the sacrificial layer;
• and
• providing an insulation layer provided on the carrier substrate, the sacrificial layer, and the conductive layer, the insulation layer comprising a photo imageable dielectric (PID).

A method of manufacturing a semiconductor package, the method comprising:

• providing a carrier substrate having a circular plate shape;
• providing a sacrificial layer on the carrier substrate;
• providing a redistribution wiring layer on the sacrificial layer;
• providing a plurality of semiconductor chips on the redistribution wiring layer;
• providing a mold layer provided on the plurality of semiconductor chips on the carrier substrate to form a wafer level stack;
• removing the sacrificial layer and the carrier substrate from the wafer level stack to expose a lower surface of the redistribution wiring layer;
• and
• dicing the wafer level stack to form the semiconductor package comprising at least one of the plurality of semiconductor chips,
• wherein the sacrificial layer comprises a release layer and a barrier layer sequentially stacked,
• wherein the redistribution wiring layer comprises a conductive layer electrically connected to the semiconductor package and an insulation layer provided on the conductive layer,
• wherein the conductive layer comprises a lower pad provided on an upper surface of the sacrificial layer, a wiring layer provided on the lower pad, and a via connecting the lower pad to the wiring layer,
• wherein the mold layer contacts an upper surface of the redistribution wiring layer, an outer side surface of the redistribution wiring layer, and a portion of the upper surface of the sacrificial layer,
• wherein the wafer level stack has a cross-sectional surface having a stepped shape,
• wherein a shortest distance between an outer side surface of the mold layer and an outer side surface of the carrier substrate is greater than a shortest distance between an outer side surface of the sacrificial layer and the outer side surface of the carrier substrate, and
• wherein the providing of the release layer comprises providing a release film on the carrier substrate and removing an edge of the release film to expose an upper surface of an edge of the carrier substrate.