Stacked three-dimensional heterogeneous memory devices and methods for forming the same

A three-dimensional (3D) memory device, comprising:

• a first semiconductor structure comprising an array of static random-access memory (SRAM) cells and a first bonding layer comprising a plurality of first bonding contacts;
• a second semiconductor structure comprising an array of dynamic random-access memory (DRAM) cells and a second bonding layer comprising a plurality of second bonding contacts;
• a third semiconductor structure comprising an array of NAND memory cells, a third bonding layer comprising a plurality of third bonding contacts, and a fourth bonding layer comprising a plurality of fourth bonding contacts, wherein the third bonding layer and the fourth bonding layer are on both sides of the array of NAND memory cells;
• a first bonding interface between the first bonding layer and the third bonding layer, the first bonding contacts being in contact with the third bonding contacts at the first bonding interface;
• and
• a second bonding interface between the second bonding layer and the fourth bonding layer, the second bonding contacts being in contact with the fourth bonding contacts at the second bonding interface.

A method for forming a three-dimensional (3D) memory device, comprising:

• forming a first semiconductor structure comprising an array of NAND memory cells and a first bonding layer comprising a plurality of first bonding contacts;
• forming a second semiconductor structure comprising an array of dynamic random-access memory (DRAM) cells and a second bonding layer comprising a plurality of second bonding contacts;
• forming a third semiconductor structure comprising an array of static random-access memory (SRAM) cells and a third bonding layer comprising a plurality of third bonding contacts;
• bonding the third semiconductor structure and one of the first and second semiconductor structures in a face-to-face manner to form a bonded structure having a first bonding interface between the third bonding layer and one of the first and second bonding layers;
• forming a fourth bonding layer comprising a plurality of fourth bonding contacts in the third semiconductor structure, wherein the third bonding layer and the fourth bonding layer are on both sides of the array of SRAM cells;
• and
• bonding the bonded structure and another one of the first and second semiconductor structures in a face-to-face manner to form a second bonding interface between the fourth bonding layer and another one of the first and second bonding layers.

The method of 16, further comprising:

• thinning the third substrate after bonding the third semiconductor structure and one of the first and second semiconductor structures;
• forming a contact extending vertically through the thinned third substrate to be in contact with the third interconnect layer;
• and
• forming the fourth bonding layer on the thinned third substrate and in contact with the contact.