Covert gates to protect gate-level semiconductors

A NOR circuit, comprising:

• a regular PMOS transistor and an always-on PMOS transistor connected in series to form a pull-up network (PUN);
• and
• a regular NMOS transistor and an always-off NMOS transistor connected in parallel to form a pull-down network (PDN), wherein the PUN and PDN are connected in series;
• wherein the always-on PMOS transistor comprises:
• an active region comprising first dopants at a first carrier concentration under a gate of the always-on PMOS transistor,
• a source and a drain comprising second dopants, and
• a layer of third dopants at a third carrier concentration arranged inside the active region, wherein the third carrier concentration of the third dopants is higher than the first carrier concentration of the first dopants, such that the always-on PMOS transistor remains in an always-on state;
• and
• wherein the always-off NMOS transistor comprises:
• an active region comprising the second dopants at a second carrier concentration under a gate of the always-off NMOS transistor,
• a source and a drain comprising the first dopants,
• a contact hole formed directly on a top of the gate of the always-off NMOS transistor, and
• a layer of dielectric material coated on a side wall and a bottom of the contact hole to insulate said gate and said source from a conductive material filled into the contact hole, such that the always-off NMOS transistor remains in an always-off state.