Methods of manufacturing semiconductor device and semiconductor device

A method of manufacturing a semiconductor device, comprising:

• forming a first interlayer dielectric (ILD) layer over a substrate;
• forming a chemical mechanical polishing (CMP) stop layer over the first ILD layer;
• forming a trench opening in a peripheral area and a via opening in a circuit area by patterning the CMP stop layer and the first ILD layer;
• forming an underlying first process mark in the peripheral area and a via contact in the circuit area by forming a first conductive layer in the trench opening and the via opening, respectively;
• forming a memory structure over the via contact;
• forming a lower dielectric layer over the underlying first process mark and the memory structure;
• forming a middle dielectric layer over the lower dielectric layer;
• forming an upper dielectric layer over the middle dielectric layer;
• performing a planarization operation on the upper, middle and lower dielectric layers so that a part of the middle dielectric layer remains over the underlying first process mark;
• and
• forming a second process mark by the lower dielectric layer by removing the remaining part of the middle dielectric layer.

A method of manufacturing a semiconductor device, comprising:

• forming a first dielectric layer over a substrate;
• forming a trench opening by patterning the first dielectric layer;
• forming an underlying first process mark by forming a first conductive layer in the trench opening;
• forming a lower dielectric layer over the underlying first process mark;
• forming a middle dielectric layer over the lower dielectric layer;
• forming an upper dielectric layer over the middle dielectric layer;
• performing a planarization operation on the upper, middle and lower dielectric layers so that a part of the middle dielectric layer remains over the underlying first process mark;
• and
• forming a second process mark by the lower dielectric layer by removing the remaining part of the middle dielectric layer.