Panel-level chip device and packaging method thereof

A panel-level chip device, comprising:

• a plurality of first bare chips disposed on a supporting base;
• a plurality of first connection pillars disposed on a side of a first bare chip of the plurality of first bare chips away from the supporting base;
• a first encapsulation layer, wherein the first encapsulation layer covers the first bare chip and the plurality of first connection pillars, and exposes a side surface of a first connection pillar of the plurality of first connection pillars away from the first bare chip;
• a first redistribution layer, disposed on a side of the first encapsulation layer away from the supporting base, wherein the first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements;
• and
• a solder ball group, disposed on a side of the first redistribution layer away from the first encapsulation layer, wherein the solder ball group includes a plurality of first solder balls,
• wherein:
• first connection pillars in the plurality of the first connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element of the plurality of first redistribution elements, and
• each of remaining first connection pillars in the plurality of the first connection pillars is electrically connected to one second redistribution element of the plurality of second redistribution elements, the one second redistribution element further being electrically connected to a first solder ball of the plurality of first solder balls.