US 11,056,426 B2Granted

Metallization interconnect structure formation

AssigneeInternational Business Machines Corporation

InventorsYann Mignot, Hosadurga Shobha, Hsueh-Chung Chen, Chih-Chao Yang

Life of this patent

Estimating the term…

Loading patent…

Abstract

Techniques for fabricating a metallic interconnect include forming a first metallization layer that includes a first dielectric layer, a first metallic layer formed in the first dielectric layer and a first capping layer formed on the first dielectric layer and the first metallic layer and forming a second metallization layer that includes a second dielectric layer, a second metallic layer formed in the second dielectric layer and a second capping layer formed on the second dielectric layer and the second metallic layer. A channel is etched in the second capping layer, second dielectric layer, and first capping layer that exposes a portion of the first metallic layer and a portion of the second metallic layer. A metallic interconnect structure is formed in the channel in contact with the exposed portion of the first metallic layer and the exposed portion of the second metallic layer.

Claims20

Dependent claims

A method for fabricating a metallic interconnect of a semiconductor device, comprising:

forming a first metallization layer of the semiconductor device, the first metallization layer comprising a first dielectric layer, a first metallic layer formed in the first dielectric layer and a first capping layer formed on the first dielectric layer and the first metallic layer;
forming a second metallization layer of the semiconductor device, the second metallization layer comprising a second dielectric layer, a second metallic layer formed in the second dielectric layer and a second capping layer formed on the second dielectric layer and the second metallic layer;
etching a channel in the second capping layer, second dielectric layer, and first capping layer, the channel exposing a portion of the first metallic layer and a portion of the second metallic layer;
forming a metallic interconnect structure in the channel, the metallic interconnect structure being formed in contact with the exposed portion of the first metallic layer and the exposed portion of the second metallic layer;
planarizing the metallic interconnect structure and the second capping layer to a surface of the second metallic layer, the planarizing removing the second capping layer;
and
forming a third capping layer over the second dielectric layer, second metallic layer, and metallic interconnect structure.

4 more elements

A method for fabricating a metallic interconnect of a semiconductor device, comprising:

forming a middle-of-line layer of the semiconductor device, the middle of line layer comprising at least one metallic contact and a first capping layer formed over the at least one metallic contact;
forming a metallization layer of the semiconductor device, the metallizatioon layer comprising a dielectric layer, a metallic layer formed in the dielectric layer and a second capping layer formed on the dielectric layer and the metallic layer;
etching a channel in the second capping layer, dielectric layer, and first capping layer, the channel exposing a portion of the metallic contact and a portion of the metallic layer;
and forming a metallic interconnect structure in the channel, the metallic interconnect structure being formed in contact with the exposed portion of the metallic contact and the exposed portion of the metallic layer;
planarizing the metallic interconnect structure and the second capping layer to a surface of the metallic layer, the planarizing removing the second capping layer;
and
forming a third capping layer over the dielectric layer, metallic layer, and metallic interconnect structure.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/425,524Filed 29 May 2019
Published: US 2020/0381354 A13 Dec 2020
Granted: 6 Jul 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs
H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 20/0693
By forming self-aligned vias or self-aligned contact plugs: by forming self-aligned vias
H10W 20/084
By forming openings in the dielectric parts: for dual-damascene structures