Semiconductor device having backside interconnect structure on through substrate via and method of forming the same

A method of forming a semiconductor device, the method comprising:

• forming on a frontside of a semiconductor substrate a transistor;
• forming a conductor extending from the frontside of the substrate into the substrate;
• recessing a backside of the substrate to expose an end of the conductor;
• conformally depositing a dielectric film over sidewalls and a top surface of the end of the conductor;
• removing the dielectric film from the top surface of the end of the conductor, while the dielectric film remains covering the sidewalls of the end of the conductor;
• depositing a conductive layer over the dielectric film and electrically contacting the top surface of the end of the conductor;
• patterning the conductive layer to form a redistribution line having a first portion extending substantially parallel to the backside of the substrate, a second portion extending substantially perpendicular to the backside of the substrate and contacting sidewalls of the dielectric film, and a third portion extending away from the second portion and extending substantially parallel to the backside of the substrate;
• conformally depositing a passivation layer over the patterned conductive layer;
• and
• patterning the passivation layer to expose a portion of the patterned conductive layer.

A method of forming a semiconductor device, the method comprising:

• forming a continuous homogenous conductor extending into a semiconductor substrate;
• recessing a surface of the semiconductor substrate to expose an end of the conductor;
• covering sidewalls of the end of the conductor with an isolation film while leaving a top surface of the end of the conductor uncovered;
• covering with a conductive layer the isolation film and the top surface of the end of the conductor;
• patterning the conductive layer;
• and
• conformally depositing a passivation layer over the patterned conductive layer;
• and
• patterning the passivation layer to cover sidewalls of the patterned conductive layer while leaving uncovered a central portion of the patterned conductive layer.