Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsAe-Nee Jang, Seung-Duk Baek, Tae-Heon Kim
Life of this patent
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Abstract
A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.
Claims19
A semiconductor package comprising:
- a package substrate;
- an interposer located over an upper surface of the package substrate and electrically connected to the package substrate;
- a logic chip located over an upper surface of the interposer and electrically connected to the interposer;
- a memory chip located over the upper surface of the interposer and electrically connected to the interposer and to the logic chip;
- and
- a heat sink in thermal contact with an upper surface of the logic chip to dissipate heat in the logic chip,
- wherein the heat sink has an upper surface coplanar with an upper surface of the memory chip.
A semiconductor package comprising:
- a package substrate;
- an interposer located over an upper surface of the package substrate and electrically connected with the package substrate;
- a logic chip located over an upper surface of the interposer and electrically connected with the interposer;
- a memory chip located over the upper surface of the interposer and electrically connected with the interposer and the logic chip, the memory chip having an upper surface that is higher than an upper surface of the logic chip;
- a heat sink making thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip, the heat sink having an upper surface that is coplanar with the upper surface of the memory chip;
- and
- a main heat sink directly making thermal contact with the upper surfaces of the memory chip and the heat sink to dissipate heat in the memory chip and the heat sink.
Dependencies are inferred from the claim text.