Method of manufacturing semiconductor package using alignment mark on wafer
AssigneeNational Institute of Advanced Industrial Science and Technology
InventorsShiro Hara, Sommawan Khumpuang, Fumito Imura
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AssigneeNational Institute of Advanced Industrial Science and Technology
InventorsShiro Hara, Sommawan Khumpuang, Fumito Imura
Estimating the term…
A method of manufacturing a semiconductor package and a semiconductor package in which positional alignment between a wafer and a substrate until the wafer is mounted and packaged on the substrate is achieved accurately. A wafer is mounted on a package substrate by using first alignment marks and D-cuts as benchmarks, and then a mold resin layer is formed on the wafer in a state in which the first alignment mark is exposed. A part of the mold resin layer is removed by using the D-cuts exposed from the mold resin layer as benchmarks, so that the first alignment marks can be visually recognized. A second alignment marks are formed on the mold resin layer by using the first alignment marks as benchmarks. A Cu redistribution layer to be conducted to a pad portion is formed on a mold resin layer by using the second alignment marks as benchmarks.
A method of manufacturing a semiconductor package for packaging a wafer including a first alignment mark and a pad portion formed on an upper surface thereof on a substrate having a larger outer shape than the wafer and including a positioning portion for positional alignment at an outer edge, the method comprising:
A method of manufacturing a semiconductor package for packaging a plurality of wafers disposed on a base substrate including a first alignment mark and a pad portion formed on an upper surface thereof on a substrate having a larger outer shape than the base substrate and including a positioning portion for positional alignment at an outer edge, the method including:
A semiconductor package comprising:
A semiconductor package comprising:
Dependencies are inferred from the claim text.