Semiconductor chips including through electrodes and methods of testing the through electrodes

A semiconductor chip comprising:

• a first semiconductor device;
• and
• a second semiconductor device stacked over the first semiconductor device and electrically connected to the first semiconductor device via a plurality of through electrodes,
• wherein in a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes, configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally, and
• wherein the detection signal indicates that the plurality of through electrodes operated normally when the detection signal is a toggling signal;
• and
• wherein the detection signal indicates that the plurality of through electrodes operated abnormally, by generating an incorrect logic level, when the detection signal has a fixed logic level.