Gate-all-around devices having gate dielectric layers of varying thicknesses and method of forming the same

An integrated circuit device, comprising:

• a core device including:
• a first channel member;
• a first gate structure engaging the first channel member, the first gate structure including a first interfacial layer wrapping a channel region of the first channel member;
• a second channel member;
• and
• a second gate structure engaging the second channel member, the second gate structure including a second interfacial layer wrapping a channel region of the second channel member, wherein a thickness of the second interfacial layer in a direction generally perpendicular to a longitudinal axis of the second channel member is greater than a thickness of the first interfacial layer in a direction generally perpendicular to a longitudinal axis of the first channel member;
• and
• an input/output (I/O) device including:
• a third channel member;
• and
• a third gate structure engaging the third channel member, the third gate structure including a third interfacial layer wrapping a channel region of the third channel member, wherein a thickness of the third interfacial layer in a direction generally perpendicular to a longitudinal axis of the third channel member is greater than the thickness of the second interfacial layer.

A method, comprising:

• providing a structure having a first channel member, a second channel member, and a third channel member, wherein the first channel member and the second channel member are located in a core region of an integrated circuit device, and the third channel member is located in an input/output (I/O) region of the integrated circuit device;
• forming, by a first process, a first oxide layer and a second oxide layer, the first oxide layer wrapping a channel region of the first channel member, the second oxide layer wrapping a channel region of the second channel member;
• forming, by a second process different from the first process, a third oxide layer wrapping a channel region of the third channel member;
• forming a first dielectric layer, a second dielectric layer, and a third dielectric layer over the first oxide layer, the second oxide layer, and the third oxide layer, respectively;
• forming a first capping layer, a second capping layer, and a third capping layer over the first dielectric layer, the second dielectric layer, and the third dielectric layer, respectively;
• removing the second capping layer to expose the second dielectric layer, wherein the first capping layer and the third capping layer respectively remain over the first dielectric layer and the third dielectric layer after the removing of the second capping layer;
• and
• after removing the second capping layer, performing an annealing process to increase a thickness of the second oxide layer.