Subtractive vFET process flow with replacement metal gate and metallic source/drain
AssigneeInternational Business Machines Corporation
InventorsHari V. Mallela, Robert Russell Robison, Reinaldo Ariel Vega, Rajasekhar Venigalla
Life of this patent
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Abstract
A method and a semiconductor device includes a substrate, and a first device type formed on the substrate, the first device type including an active channel region including a first fin, the first fin including a first fin width which is narrower than a second fin width above and below the active channel region. A second device type can be formed on the same substrate, the second device type includes a second active channel region including a second fin, the second fin including a first fin width which is the same as the second fin width both above and below the second active channel region.
Claims3
A semiconductor device, comprising:
- a substrate;
- a first device type formed on the substrate, the first device type comprising a first active channel region including a first fin, the first fin comprising a first fin width which is narrower than a second fin width of the first fin towards above and below the first active channel region, and
- a second device type formed on the substrate, the second device type comprising a second active channel region including a second fin of a different configuration than the first fin with respect to fin widths,
- wherein the first device type further comprises a gate dielectric stack covering a surface of the first active channel region, a top surface of the second fin width being above the first active channel region, and a bottom surface of the second fin width being below the first active channel region,
- further comprising a top portion and a bottom portion of sidewall spacers comprising a first dielectric covering the second fins above and below the second active channel region and a second dielectric covering the first dielectric.
A semiconductor device, comprising:
- a first fin being formed in a first active channel region of a first device type on a substrate,
- wherein a first fin width is narrower than a second fin width of the first fin towards above and below the first active channel region;
- and
- a second fin being formed of a different configuration than the first fin with respect to fin widths,
- wherein the first device type includes the first fin,
- wherein a second device type includes the second fin,
- wherein the first device type further comprises:
- a gate region that is merged between adjacent fins including the first fin;
- and
- a bottom source-drain region formed on the substrate and below the first fin, the bottom source-drain region comprising a metallic material;
- and
- further comprising a top portion and a bottom portion of sidewall spacers comprising a first dielectric covering the second fin above and below the second active channel region and a second dielectric covering the first dielectric,
- wherein the first dielectric is formed thicker than a interlayer dielectric,
- wherein a thinner portion of the first fin is self-aligned to the gate, and
- wherein one of the first fins under a top sidewall portion of the spacers has a width that is different than the width of another one of the first fins under a bottom sidewall portion of the spacers.
Dependencies are inferred from the claim text.