Track-and-hold circuit

A track-and-hold circuit performing switching, by using a clock signal, between a track mode in which a data signal that is equivalent to an input data signal is output and a hold mode in which a data signal which is input at a time of switching from the track mode to the hold mode is held and output, such that only the data signal in the hold mode is output, the track-and-hold circuit comprising:

• two sampling circuits configured to be connected in parallel to an input of the data signal and receive an in-phase data signal;
• a first clock circuit configured to input a clock signal, which has a phase opposite to a phase of a clock signal input to one of the two sampling circuits, to the other of the two sampling circuits;
• a second clock circuit configured to input a second clock signal different from the clock signal to a sampling circuit;
• and
• a multiplexer circuit configured to select and output a data output of either one of the two sampling circuits that is in the hold mode, by using the second clock signal.

A track-and-hold circuit configured to switch between a track mode in which a data signal that is equivalent to an input data signal is output and a hold mode in which a data signal which is input at a time of switching from the track mode to the hold mode is held and output, such that only the data signal in the hold mode is output, the track-and-hold circuit comprising:

• a first sampling circuit having a first input and a second sampling circuit having a second input, wherein the first and second sampling circuits are connected in parallel, wherein the first and second sampling circuits are configured to receive an in-phase data signal at the first input and at the second input;
• a clock circuit configured to input a clock signal to the first sampling circuit and input a clock signal to the second sampling circuit, wherein the clock signal input to the first sampling circuit has a phase opposite to a phase of the clock signal input to the second sampling circuit;
• and
• a multiplexer circuit configured to select and output a data output of either one of the first and second sampling circuits that is in the hold mode using the clock circuit,
• wherein one or more current sources among current sources used in the first and second sampling circuits are shared between the first and second sampling circuits.