Memory device and write method thereof
AssigneeMacronix International Co., Ltd.
InventorsYa-Jui Lee, Kuan-Fu Chen
Life of this patent
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Abstract
A memory device and a write method thereof are provided. A control circuit performs a first write operation and a first write verification operation on a plurality of memory cells of a non-volatile memory, and after the plurality of memory cells pass the first write verification operation, the control circuit performs a second write verification operation on target memory cells corresponding to at least one target threshold voltage in the plurality of memory cells, and when a failure bit count of the target memory cells is not less than a preset number of bits, the control circuit performs a second write operation and a third write verification operation on the plurality of memory cells.
Claims14
A memory device, comprising:
- a non-volatile memory;
- and
- a control circuit performing a first write operation and a first write verification operation on a plurality of memory cells of the non-volatile memory, wherein after the plurality of memory cells pass the first write verification operation, the control circuit performs a second write verification operation on target memory cells corresponding to at least one target threshold voltage in the plurality of memory cells, when a failure bit count of the target memory cells is not less than a preset number of bits, the control circuit performs a second write operation and a third write verification operation on the plurality of memory cells.
A write method of a memory device, the memory device comprising a plurality of memory cells, the write method of the memory device comprising:
- performing a first write operation and a first write verification operation on the plurality of memory cells;
- after the plurality of memory cells pass the first write verification operation, performing a second write verification operation on target memory cells corresponding to at least one target threshold voltage in the plurality of memory cells;
- determining whether a failure bit count of the target memory cells is less than a preset number of bits;
- if the failure bit count of the target memory cells is not less than the preset number of bits, performing a second write operation and a third write verification operation on the plurality of memory cells.
Dependencies are inferred from the claim text.