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AssigneeIntel Corporation
InventorsXiang Yang, Pranav Kalavade, Ali Khakifirooz, Shantanu R. Rajwade, Sagar Upadhyay
Estimating the term…
In one aspect of programmed state verification in accordance with the present description, the voltage levels on bitlines of non-target storage cells are each boosted by applying a non-zero offset or delta value, ΔV, to the bitlines of non-target storage cells during a precharge subinterval. A bitline verification voltage applied to a bitline of a target storage cell causes the voltage of the bitline to ramp up from the boosted ΔV value. As a result, starting from an initial value which is the higher or boosted ΔV value, the bitline voltage ramps up more quickly during the precharge subinterval to the bitline verification voltage level to improve system performance. In addition, the bitline verification voltage applied to bitlines of target storage cells during the precharge subinterval, can be at a relatively high value to maintain the accuracy of program state verification.
An apparatus for use with a memory array of storage cells having bitlines, comprising:
A method, comprising:
A system, comprising:
Dependencies are inferred from the claim text.