Semiconductor memory device capable of shortening erase time
AssigneeToshiba Memory Corporation
InventorNoboru Shibata
Life of this patent
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Abstract
In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k(k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
Claims12
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are connected to a plurality of word lines and a plurality of bit lines;
- and
- a control circuit which controls the potentials of the plurality of word lines and the plurality of bit lines,
- wherein, in an erase operation, the control circuit erases the plurality of memory cells connected to n word lines of the plurality of word lines simultaneously, and carries out a verify operation for m memory cells in the n word lines using a first verify level and a counting operation to determine whether the threshold voltage of k(k≤m) number of memory cells has reached a threshold level in the erase operation.
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells are connected to a plurality of word lines and a plurality of bit lines;
- and
- a control circuit which controls the potentials of the plurality of word lines and the plurality of bit lines,
- wherein, in an erase operation, the control circuit erases the plurality of memory cells connected to n word lines of the plurality of word lines simultaneously and then performs a write operation on the plurality of memory cells connected to the n word lines simultaneously, and carries out a verify operation for m memory cells in the n word lines using a first verify level and a counting operation to determine whether the threshold voltage of k(k≤m) number of memory cells has reached a threshold level in the erase operation.
Dependencies are inferred from the claim text.