Apparatus for determining data states of memory cells

A memory, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells, wherein a first subset of strings of series-connected memory cells of the plurality of strings of series-connected memory cells is programmed to contain a pattern of data representative of a first data state of a plurality of data states, and wherein a second subset of strings of series-connected memory cells of the plurality of strings of series-connected memory cells is programmed to contain a pattern of data representative of a second data state of the plurality of data states;
• a plurality of access lines, each access line of the plurality of access lines connected to a respective plurality of memory cells comprising a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
• and
• a controller for access of the array of memory cells, wherein the controller, during a read operation on the plurality of strings of series-connected memory cells, is configured to cause the memory to:
• increase a voltage level applied to each access line of the plurality of access lines;
• determine a first read voltage level corresponding to a voltage level applied to each access line of the plurality of access lines at which each memory cell of the first subset of strings of series-connected memory cells is deemed to be activated while increasing the voltage level applied to each access line of the plurality of access lines;
• determine a second read voltage level corresponding to a voltage level applied to each access line of the plurality of access lines at which each memory cell of the second subset of strings of series-connected memory cells is deemed to be activated while increasing the voltage level applied to each access line of the plurality of access lines;
• for a subset of memory cells of the respective plurality of memory cells for a particular access line, determine which memory cells of the subset of memory cells are deemed to be activated in response to applying the first read voltage level to the particular access line, and determine which memory cells of the subset of memory cells are deemed to be deactivated in response to applying the first read voltage level to the particular access line and activated in response to applying the second read voltage level to the particular access line.

A memory, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells, wherein the plurality of strings of series-connected memory cells comprises M first subsets of strings of series-connected memory cells of the plurality of strings of series-connected memory cells and one second subset of strings of series-connected memory cells of the plurality of strings of series-connected memory cells, wherein M is an integer value greater than or equal to 2, and wherein the M first subsets of strings of series-connected memory cells are each programmed to contain a respective pattern of data representative of a respective data state of M data states;
• a plurality of access lines, each access line of the plurality of access lines connected to a respective plurality of memory cells comprising a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
• and
• a controller for access of the array of memory cells, wherein the controller, during a read operation on the plurality of strings of series-connected memory cells, is configured to cause the memory to:
• increase a voltage level applied to each access line of the plurality of access lines;
• for N=1 to M−1, determine an Nth voltage level corresponding to a voltage level applied to each access line of the plurality of access lines at which each memory cell of a particular access line of strings of series-connected memory cells is deemed to be activated while increasing the voltage level applied to each access line of the plurality of access lines;
• for at least one value of N=1 to M−1, determine which memory cells, of a subset of memory cells of the respective plurality of memory cells for the particular access line corresponding to the second subset of strings of series-connected memory cells, are deemed to be activated in response to applying the Nth voltage level to the particular access line, and which memory cells of the subset of memory cells are deemed to be deactivated in response to applying the Nth voltage level to the particular access line.