Nonvolatile memory device and method of controlling initialization of the same

A method of controlling initialization of a nonvolatile memory device, the nonvolatile memory device comprising a memory cell region including a first metal pad and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, the method comprising:

• performing a first sensing operation to sense a write setting data stored in first memory cells in the memory cell region of a first memory plane and store first read setting data in a first page buffer circuit in the peripheral circuit region of the first memory plane;
• performing a second sensing operation to sense the write setting data stored in second memory cells in the memory cell region of a second memory plane and store second read setting data in a second page buffer circuit in the peripheral circuit region of the second memory plane;
• verifying validity of each of a plurality of first data units using a first verification circuit connected to the first page buffer circuit, the plurality of first data units corresponding to the first read setting data divided by a unit bit number;
• verifying validity of each of a plurality of second data units using a second verification circuit connected to the second page buffer circuit, the plurality of second data units corresponding to the second read setting data divided by the unit bit number;
• selectively enabling the first verification circuit and the second verification circuit based on a validity verification result of each of the plurality of first data units and a validity verification result of each of the plurality of second data units;
• and
• storing a valid data unit corresponding to one of a first data unit and a second data unit in a buffer based on the validity verification result of each of the plurality of first data units and the validity verification result of each of the plurality of second data units.

A nonvolatile memory device comprising:

• a memory cell region including a first metal pad;
• a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
• a first memory plane including first memory cells in the memory cell region storing write setting data and a first page buffer circuit in the peripheral circuit region storing first read setting data sensed from the first memory cells;
• a second memory plane including second memory cells in the memory cell region storing the write setting data and a second page buffer circuit in the peripheral circuit region storing second read setting data sensed from the second memory cells;
• a first verification circuit connected to the first page buffer circuit, the first verification circuit configured to verify validity of the first read setting data;
• a second verification circuit connected to the second page buffer circuit, the second verification circuit configured to verify validity of the second read setting data;
• a dump-down control logic configured to determine valid data corresponding to one of the first read setting data and the second read setting data based on a validity verification result of the first read setting data and a validity verification result of the second read setting data;
• and
• a buffer configured to store the valid data provided from the dump-down control logic.