Charge pump and memory device including the same

A memory device comprising:

• a memory cell region including a first metal pad;
• a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
• a memory cell array in the memory cell region including a plurality of cell strings including a plurality of memory cells, a plurality of word lines respectively connected to the plurality of memory cells, a plurality of bit lines connected to one side of the plurality of cell strings, and a ground selection line connected to the plurality of cell strings;
• a first pumping capacitor in the peripheral circuit region comprising one end connected to a first node and an other end configured to receive a first clock signal;
• a second pumping capacitor in the peripheral circuit region comprising one end connected to a second node and an other end configured to receive a second clock signal that is complementary with the first clock signal;
• a charging unit in the peripheral circuit region comprising a first n-type transistor configured to charge the first pumping capacitor with an input voltage based on the first clock signal, and a second n-type transistor configured to charge the second pumping capacitor with the input voltage based on the second clock signal;
• and
• an output unit in the peripheral circuit region connected to the charging unit via the first node and the second node, the output unit configured to alternately output node voltages of the first node and the second node to an output terminal in response to the first clock signal and the second clock signal,
• wherein a bulk of each of the first n-type transistor and the second n-type transistor is formed in a portion of a deep-n well formed on a p-type semiconductor substrate, and
• wherein a voltage greater than or equal to a voltage applied to the p-type semiconductor substrate is applied to the deep-n well responsive to operation of the charge pump.

A memory device comprising:

• a memory cell region including a first metal pad;
• a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
• a memory cell array in the memory cell region including a plurality of cell strings including a plurality of memory cells, a plurality of word lines respectively connected to the plurality of memory cells, a plurality of bit lines connected to one side of the plurality of cell strings, and a ground selection line connected to the plurality of cell strings;
• a control logic in the peripheral circuit region configured to output a control signal that controls a program operation of programming data in the memory cell array and a read operation of reading data from the memory cell array;
• and
• a voltage generator in the peripheral circuit region configured to generate operation voltages used for the program operation and the read operation in response to the control signal,
• wherein the voltage generator comprises:
• a charging unit comprising a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal, and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal;
• a first pumping capacitor comprising one end connected to the first node and an other end configured to receive the first clock signal;
• a second pumping capacitor comprising one end connected to the second node and an other end configured to receive the second clock signal;
• and
• an output unit connected between the charging unit and an output terminal, the output unit configured to output a first voltage at the first node or a second voltage at the second node to the output terminal,
• wherein a bulk of each of the first n-type transistor and the second n-type transistor is formed in a portion of a deep-n well formed on a p-type semiconductor substrate, and
• wherein a voltage greater than or equal to a voltage applied to the p-type semiconductor substrate is applied to the deep-n well responsive to operation of the charge pump.