Nonvolatile memory device and related driving method

A driving method of a nonvolatile memory device comprising a plurality of memory planes comprises:

• precharging at least one word line and at least one bit line of a first memory plane of the plurality of memory planes;
• if the at least one word line and the at least one bit line of the first memory plane have been precharged for a second time length shorter than a first time length, precharging at least one word line and at least one bit line of a second memory plane of the plurality of memory planes while continuing precharging the at least one word line and the at least one bit line of the first memory plane;
• when the at least one word line and the at least one bit line of the first memory plane have been precharged for the first time length, conducting a first data operation to at least one memory cell of the first memory plane, wherein the at least one memory cell of the first memory plane is disposed at intersections of the at least one word line and the at least one bit line of the first memory plane;
• and
• when the at least one word line and the at least one bit line of the second memory plane have been precharged for the first time length, conducting a second data operation to at least one memory cell of the second memory plane, wherein the at least one memory cell of the second memory plane is disposed at intersections of the at least one word line and the at least one bit line of the second memory plane.

A nonvolatile memory device, comprising:

• a memory chip, comprising a plurality of memory planes;
• and
• a control circuit, coupled with the memory chip, and being adapted to:
• precharge at least one word line and at least one bit line of a first memory plane of the plurality of memory planes;
• if the at least one word line and the at least one bit line of the first memory plane have been precharged for a first time length or to respective voltage thresholds, precharge at least one word line and at least one bit line of a second memory plane of the plurality of memory planes;
• conduct a first data operation to at least one memory cell of the first memory plane, wherein the at least one memory cell of the first memory plane is disposed at intersections of the at least one word line and the at least one bit line of the first memory plane;
• and
• conduct a second data operation to at least one memory cell of the second memory plane, wherein the at least one memory cell of the second memory plane is disposed at intersections of the at least one word line and the at least one bit line of the second memory plane.