Three dimensional nonvolatile memory device including channel structure and resistance change memory layer
AssigneeSK hynix Inc.
InventorsJae Hyun Han, Hyangkeun Yoo, Se Ho Lee
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Abstract
A nonvolatile memory device includes a substrate, a source electrode structure disposed on the substrate, a channel structure disposed to be contact a sidewall surface of the source electrode structure, a resistance change memory layer disposed on a sidewall surface of the channel structure, a drain electrode structure disposed to contact the resistance change memory layer, a plurality of gate dielectric structures extending in the first direction and disposed to be spaced apart from each other in a second direction, and a plurality of gate electrode structures disposed to extend in the first direction in the plurality of the gate dielectric structure.
Claims22
A nonvolatile memory device comprising:
- a substrate;
- a source electrode structure disposed on the substrate, the source electrode structure comprising a plurality of source electrode layers and a plurality of source insulation layers that are alternately stacked in a first direction perpendicular to the substrate, wherein the source electrode structure extends in a second direction perpendicular to the first direction,
- a channel structure disposed on the substrate and disposed to contact a sidewall surface of the source electrode structure, the sidewall surface of the source electrode structure being a plane formed by the first and second directions;
- a resistance change memory layer disposed on a sidewall surface of the channel structure on the substrate, the sidewall surface of the channel structure being a plane formed by the first and second directions;
- a drain electrode structure, disposed to contact the resistance change memory layer on the substrate, comprising a plurality of drain electrode layers and a plurality of drain insulation layers that are alternately disposed in the first direction, wherein the drain electrode structure extends in the second direction;
- a plurality of gate dielectric structures extending in the first direction and disposed to be spaced apart from each other in the second direction;
- and
- a plurality of gate electrode structures disposed to extend in the first direction in the gate dielectric structure,
- wherein the plurality of source electrode layers and the plurality of drain electrode layers are disposed respectively on a plurality different planes that intersect with the plurality of gate electrode structures.
A nonvolatile memory device comprising:
- a substrate;
- a global source line, the global source line comprising a plurality of source electrode layers spaced apart from each other in a first direction perpendicular to the substrate, wherein the plurality of source electrode layers extend in a second direction perpendicular to the first direction;
- a channel structure disposed on the substrate to contact the global source line in a third direction perpendicular to the first and second directions;
- a resistance change memory layer disposed to contact a sidewall surface of the channel structure in the third direction;
- a global drain line disposed to contact the resistance change memory layer in the third direction on the substrate, the global drain line comprising a plurality of drain electrode layers disposed to be spaced apart from each other in the first direction, wherein the plurality of drain electrode layers extend in the second direction;
- a plurality of gate dielectric structures extending in the first direction in the channel structure and disposed to be spaced apart from each other in the second direction;
- and
- a plurality of gate electrode structures in the plurality of gate dielectric structures, extending in the first direction,
- wherein the channel structure is separated from one of the plurality of gate electrode structures by one of the plurality of the gate dielectric structures,
- wherein the plurality of source electrode layers and the plurality of drain electrode layers are disposed respectively on a plurality different planes that intersect with the plurality of gate electrode structures.
Dependencies are inferred from the claim text.