Apparatus for deep learning operations on resistive crossbar array

A circuit for both forward and reverse read operations on a neuromorphic crossbar array that is part of an artificial neural network (ANN), wherein a synaptic weight of each synapse in the ANN is represented by a pair of conductances, G+ and G-, respectively, the circuit comprising:

• (a) a cell access transistor for each cell of the ANN, a gate terminal of the cell access transistor connected to a word line (WL) of the array, wherein the cell access transistor, in a forward read operation, carries a pulse width signal encoding an activation of a single neuron in the ANN;
• (b) a source-follower transistor for each cell of the ANN, which in a forward read operation is biased at a source follower voltage (VRDP) to hold a column voltage node (BLV) at read voltage (VREAD), and which in a reverse read operation is disconnected;
• (c) a resistive element connecting the cell access transistor and the source follower transistor, wherein the conductance of the resistive element represents either the positive weight contribution conductance, G+, or the negative weight contribution conductance, G-;
• wherein the cell access transistor, in a reverse read operation, operates as another source follower by:
• encoding a neuron error signal into the column voltage node (BLV), driving the word line of the cell access transistor to the source follower voltage (VRDP), and holding an intermediate node between the cell access transistor of (a) and the source follower transistor of (b) at the read voltage (VREAD), and wherein an OFF-state voltage of the column voltage node (BLV) is to be larger than the source follower voltage (VRDP) to eliminate current leakage, and an ON-state voltage of the column voltage node (BLV) is to be at ground (GND) so that a current versus conductance behavior is linear over a predetermined range of conductance values.

A method for both forward and reverse read operations in a neuromorphic crossbar array that is part of an artificial neural network (ANN), the method comprising:

• (a) during a forward read operation, encoding a plurality of neuron activations into a pulse width drive array word line that gates a cell access transistor;
• (b) biasing a source-follower transistor at a source follower voltage (VRDP) and holding a column voltage node (BLV) at read voltage (VREAD);
• and (c) during a reverse read operation, operating the cell access transistor as another source follower by:
• encoding a neuron error signal into the column voltage node (BLV), driving the word line of the cell access transistor to the source follower voltage (VRDP), and holding an intermediate node between the cell access transistor of (a) and the source follower transistor of (b) at the read voltage (VREAD).