Multi-port memory circuitry
AssigneeArm Limited
InventorsYew Keong Chong, Andy Wangkun Chen, Sriram Thyagarajan
Life of this patent
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Abstract
Various implementations described herein are directed to an integrated circuit having multiple bitcell arrays and multiple input ports including a single write input port for the multiple bitcell arrays and multiple read input ports for the multiple bitcell arrays. The integrated circuit may include multiple read output ports for the multiple bitcell arrays. The single write input port is used for writing data to the multiple bitcell arrays, and the multiple read input ports are used separately for reading data from the multiple bitcell arrays for output to the multiple read output ports.
Claims14
An integrated circuit, comprising:
- multiple bitcell arrays including a first bitcell array and a second bitcell array that is separate from the first bitcell array, wherein each bitcell in the multiple bitcell arrays has a single write port and a single read port;
- multiple input ports including a single write input port for the multiple bitcell arrays and multiple read input ports for the multiple bitcell arrays;
- and
- multiple read output ports for the multiple bitcell arrays,
- wherein the single write input port is used for writing data to the first bitcell array or the second bitcell array, and
- wherein the multiple read input ports have a first read input port used for reading data from the first bitcell array and a second read input port used for reading data from the second bitcell array.
A method, comprising:
- providing memory circuitry with multiple bitcell arrays including a first bitcell array and a second bitcell array separate from the first bitcell array, wherein each bitcell in the multiple bitcell arrays has a write port and a read port;
- merging the multiple bitcell arrays by combining the write ports of each bitcell in the multiple bitcell arrays into a single write port;
- writing data to at least one of the multiple bitcell arrays including the first bitcell array or the second bitcell array with the single write input port;
- designating a separate read input port to communicate with the read port of each bitcell array of the multiple bitcell arrays;
- and
- manufacturing, or causing to be manufactured, the memory circuitry.
Dependencies are inferred from the claim text.