Word line pulse width control circuit in static random access memory

A static random access memory (SRAM) device comprising:

• at least two decoder driver circuits electrically coupled together via a common decoder line;
• a transistor electrically coupled to the at least two decoder driver circuits via the common decoder line;
• and
• an inverter electrically coupled to the transistor, and
• wherein the transistor charges a load of the common decoder line so as to reduce an effective load of the at least two decoder driver circuits and wherein the common decoder line is coupled to one or more transistors within each decoder driver circuit.

A method in a static random access memory (SRAM) device comprising:

• generating a first input comprising a clocked address;
• receiving, by an inverter, the clocked address;
• determining, by the inverter, an output based on the clocked address;
• modifying an electrical load of a decoder driver circuit of the SRAM device based on the output;
• and
• providing current to a transistor coupled at a common node configured to electrically couple a plurality of transistors within the decoder driver circuit.