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US 11,056,180 B2Granted
Non-volatile memory data bus
AssigneeSTMicroelectronics (Rousset) SAS
InventorFrancesco La Rosa
Life of this patent
Estimating the term…
Abstract
A non-volatile memory integrated circuit has a memory plane organized into rows and into columns containing bit lines. The read amplifiers for each bit line are configured to generate an output signal on a read data channel. The read data channels respectively run through the memory plane along each bit line. Each read data channel is connected to all of the read amplifiers of the respective bit line.
Claims21
A non-volatile memory integrated circuit, comprising:
- a memory plane organized into rows and into columns containing bit lines;
- read amplifiers for each bit line that are configured to generate an output signal on a read data channel;
- a multiplexing element for each bit line that is configured to provide a data signal on an output bus of the non-volatile memory integrated circuit based on the output signals delivered by the read amplifiers of the bit line;
- wherein the read data channels respectively run through the memory plane along each bit line;
- and
- wherein each read data channel is connected to all of the read amplifiers of the respective bit line.
3 more elements
A non-volatile memory integrated circuit, comprising:
- a memory plane organized into rows and into columns containing bit lines;
- a read amplifier coupled to each bit line and configured to generate an output signal on a read data channel;
- an interconnect portion extending above the memory plane and comprising a stack of metal levels, wherein at least one metal level includes metal tracks, said metal tracks extending parallel to the bit lines in said columns to form read data channels;
- and
- wherein each read data channel is connected to all of the read amplifiers of the respective bit line.
2 more elements
Dependencies are inferred from the claim text.