Semiconductor memory device and memory module including the same

A memory system comprising:

• a semiconductor memory device;
• a memory controller configured to issue an operation command and an address to the semiconductor memory device to write data in the semiconductor memory device and read data from the semiconductor memory device;
• and
• a channel through which data sent between the semiconductor memory device and the memory controller is transmitted,
• wherein the memory controller includes:
• a host security controller configured to encrypt write data to be stored in the semiconductor memory device to generate encrypted data and decrypt the encrypted data read from the semiconductor memory device, and
• wherein the semiconductor memory device includes:
• a buffer semiconductor die;
• a plurality of memory semiconductor dies stacked with the buffer semiconductor die, each memory semiconductor die including a memory cell array;
• through-silicon vias electrically connecting the buffer semiconductor die and the plurality of memory semiconductor dies;
• an on-chip processor formed in a first memory semiconductor die of the memory semiconductor dies, configured to perform on-chip data processing with respect to input data in order to provide result data;
• and
• a memory security controller formed in the first memory semiconductor die and configured to decrypt the encrypted data, to provide the decrypted data as the input data to the on-chip processor, to received unencrypted result data from the on-chip processor, which result data is based on the input data, to encrypt the result data from the on-chip processor to form re-encrypted data, and to provide the re-encrypted data to the first memory semiconductor die.

A method of performing secure operations for a semiconductor memory device having at least a first memory chip having a memory core including a plurality of memory cells, the method comprising:

• issuing, at a memory controller external to the semiconductor device, an operation command and an address to the semiconductor memory device to write data in the semiconductor memory device and read data from the semiconductor memory device;
• based on the operation command and the address, encrypting, at the memory controller, write data to be stored in the semiconductor memory device to generate encrypted data;
• decrypting, at the memory controller, the encrypted data read from the semiconductor memory device and transmitted through a channel connecting the memory controller and the semiconductor memory device;
• decrypting, at the first memory chip, the encrypted data provided from the memory core or from the memory controller;
• performing an on-chip processing operation by an on-chip processor of the first memory chip, by receiving the decrypted data, and outputting an unencrypted result data, the result data based on the decrypted data;
• and
• encrypting, at the first memory chip, the result data from the on-chip processor to provide respective result-encrypted data to the memory core.