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US 11,056,170 B2Granted
Semiconductor device providing an output in response to a read command or a mode-register read command
AssigneeMicron Technology, Inc.
InventorTakayuki Miyamoto
Life of this patent
Estimating the term…
Abstract
Disclosed herein is an apparatus that includes a first circuit that activates first and second timing signals in response to a first command and activates the second timing signal in response to a second command, a second circuit that amplifies a first data read out from a first memory area in response to the first command in synchronization with the first timing signal, and a third circuit that outputs one of the first data output from the second circuit and a second data read out from a second memory area in response to the second command, in synchronization with the second timing signal.
Claims18
An apparatus comprising:
- a memory cell array;
- a mode register storing a setting parameter;
- a command control circuit that activates a timing signal in response to a mode-register read command;
- a FIFO circuit that outputs the setting parameter read out from the mode register in response to the timing signal;
- a signal line for transmitting the timing signal,
- wherein the signal line includes:
- a first line section having one end connected to the command control circuit, the first line section including a portion extending along the memory cell array;
- and
- a second line section having one end connected to another end of the first line section and another end of the second line section connected to the FIFO circuit, the second line section including a portion extending along the first line section;
- and
- a delay circuit inserted into the signal line, wherein the delay circuit delays the timing signal.
8 more elements
An apparatus comprising:
- a memory cell array;
- a mode register storing a setting parameter;
- a command control circuit that activates a timing signal in response to a mode-register read command;
- a FIFO circuit that outputs the setting parameter read out from the mode register in response to the timing signal;
- a signal line for transmitting the timing signal,
- wherein the signal line includes:
- a first line section having one end connected to the command control circuit, the first line section including a portion extending along the memory cell array;
- and
- a second line section having one end connected to another end of the first line section and another end of the second line section connected to the FIFO circuit, the second line section including a portion extending along the first line section;
- and
- a read/write amplifier that outputs a read data read out from the memory cell array to the FIFO circuit in synchronization with the timing signal, wherein the read/write amplifier is activated in response to another timing signal different from the timing signal.
8 more elements
An apparatus comprising:
- a memory cell array;
- a mode register storing a setting parameter;
- a command control circuit that activates a timing signal in response to a mode-register read command;
- a FIFO circuit that outputs the setting parameter read out from the mode register in response to the timing signal;
- a signal line for transmitting the timing signal,
- wherein the signal line includes:
- a first line section having one end connected to the command control circuit, the first line section including a portion extending along the memory cell array;
- and
- a second line section having one end connected to another end of the first line section and another end of the second line section connected to the FIFO circuit, the second line section including a portion extending along the first line section;
- and
- a read/write amplifier that outputs a read data read out from the memory cell array to the FICO circuit in synchronization with the timing signal, wherein the reas/write amplifier outputs the read data to the FIFO circuit in synchronization with the timing signal supplied from the first line section.
8 more elements
A method comprising:
- receiving a mode register read command at a command control circuit;
- responsive to the mode register read command:
- activating a first timing signal with the command control circuit;
- activating a selection signal with the command control circuit;
- responsive to the selection signal, providing a setting parameter from a mode register;
- delaying the first timing signal;
- receiving the setting parameter at a FIFO circuit;
- and
- responsive to receiving the delayed first timing signal;
- providing the setting parameter from the FIFO circuit to an IO circuit.
7 more elements
A method comprising:
- receiving a read command at a command control circuit;
- responsive to the read command, activating a first timing signal with the command control circuit;
- delaying the first timing signal a first amount;
- receiving read data at a FIFO circuit responsive to the delayed first timing signal;
- and
- responsive to receiving the delayed first timing signal, providing the read data from the FIFO circuit to an IO circuit.
3 more elements
Dependencies are inferred from the claim text.